Field of the Invention
The present invention relates to an information processing apparatus having a dynamically partially reconfigurable circuit, and a control method for the information processing apparatus.
Description of the Related Art
Reconfigurable circuits are widely known, including a programmable logic device (PLD) and a field programmable gate array (FPGA), both allowing configurations of internal logic circuits to be changed. In general, the PLD and the FPGA each perform switching of internal logic blocks, by writing circuit configuration information stored in a nonvolatile memory such as a read only memory (ROM) to a configuration memory, i.e., an internal volatile memory, upon activation. Information stored in the configuration memory is cleared at the time of power-off, and therefore, it is necessary to perform reconfiguration by writing the circuit configuration information to the configuration memory again, at the time of power-on. A method for thus configuring hardware resources only once is referred to as static reconfiguration. On the other hand, devices capable of changing circuit configurations during circuit operation have also been developed, and a method for changing a logic circuit during operation is referred to as dynamic reconfiguration.
One type of FPGAs allows rewriting of only a specific area, not the entire chip, and such rewriting is referred to as partial reconfiguration. In particular, performing partial reconfiguration without stopping other circuits in operation is referred to as dynamic partial reconfiguration. In the dynamic partial reconfiguration, partial reconfiguration of logic blocks inside the FPGA can be implemented by rewriting only a part of a configuration memory area, instead of rewriting the entire configuration memory at the time of dynamic reconfiguration.
Using such a dynamic partial reconfiguration technique, circuits can be implemented in one area by switching from one to another. Therefore, it is possible to change a function implemented by a logic block, by performing time-division multiplexing of hardware resources. As a result, various functions can be flexibly implemented with small hardware resources according to a purpose while high computing performance by hardware is maintained. In Japanese Patent Application Laid-Open No. 2001-320271, this dynamic partial reconfiguration is used, so that a function can be implemented by rewriting only some of logic circuits in a FPGA. Therefore, the time taken for reconfiguration can be reduced, as compared with a conventional technique with which the entire FPGA is reconfigured.
Other techniques for reducing the time taken for reconfiguration of logic circuits are also discussed. Japanese Patent Application Laid-Open No. 2012-234337 discusses a technique for predicting processing highly likely to be executed next, during image processing. In this technique, configuration data (hereinafter referred to as “circuit configuration information”) for implementing the predicted processing is transferred beforehand to a high-speed memory. This is referred to as preload. The preload can reduce the time for transferring the circuit configuration information during the image processing, and thereby enhance the speed of the image processing.
Combining the partial reconfiguration technique with the preload technique can greatly reduce the time taken for reconfiguration, as compared with the conventional FPGA reconfiguration. Therefore, time-division multiplexing with further segmentation can be achieved.
However, segmenting a functional unit leads to an increase in the number of pieces of necessary circuit configuration information. As a result, a miss-hit rate of the preloaded circuit configuration information increases. The miss-hit described here is a case where necessary circuit configuration information is not transferred, or transferred circuit configuration information for a specific partial reconfiguration portion is not available because the relevant area is being used.
The increase in the miss-hit rate of the preloaded circuit configuration information leads to degradation of the efficiency of the image processing.
As described above, in a configuration using a partially reconfigurable circuit while partially reconfiguring the circuit, if circuit configuration information recorded in an information holding unit cannot be used, efficiency decreases, which is a problem.
For example, assume that processing of a certain function is desired to be started. Although circuit configuration information for a specific partial reconfiguration portion of the function is preloaded (transferred), the relevant area may be being used for other processing. In this situation, the relevant area cannot be reconfigured and therefore, processing stops. In this way, even if circuit configuration information for processing of a function is already transferred, the miss-hit may occur depending on for which partial reconfiguration portion the circuit configuration information for the processing of the function is provided.